1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof and more particularly to a nonvolatile semiconductor memory device a memory cell of which contains a memory transistor and a select transistor and a manufacturing method thereof.
2. Description of the Related Art
Flash memories that are nonvolatile semiconductor memory devices can be divided into two groups. One is flash memories comprising solely 1-Tr type transistors (FIG. 4A) wherein only one transistor is contained in each memory cell, and the other, flash memories comprising 2-Tr type transistors (FIG. 4B) wherein two transistors, a memory transistor and a select transistor, are contained in each memory cell.
While a flash memory comprising solely 1-Tr type transistors (referred to as `a 1-Tr type flash memory`, hereinafter) is used, if anything, with the object of reducing a cell area and attaining a high density, a flash memory comprising 2-Tr type transistors (referred to as `a 2-Tr type flash memory`, hereinafter) is often used for the purpose of achieving high-speed reading, especially where is embedded in high-speed logic devices.
The 2-Tr type flash memory contains two sorts of transistors, a memory transistor having a floating gate electrode (FG) and a control gate electrode (CG) and a select transistor. The memory transistor functions as a memory through changing the threshold value of the memory transistor, which is brought about by injection and extraction of electrons over the FG.
Since the precise adjustment of the threshold value for a transistor is generally difficult to achieve, even with the verification performed, the variation of the threshold values is often larger than 0.5 V.
In a 1-Tr type flash memory comprising only 1-Tr type transistors and, thus, containing memory transistors alone, enhancement type transistors cannot be employed as memory transistors, if the on-off characteristic is to be maintained. Therefore, with such a variation of the threshold values present, reading must be performed by transistors some of which have high threshold values or slow operational speeds so that the reading speed of the flash memory becomes considerably slow.
As against this, in the case of a 2-Tr type flash memory, even though memory transistors become enhancement type transistors by extraction of electrons out of the FGs, select transistors can serve as switches, and the on-off characteristic of the flash memory can be secured. Because the standard MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor) are used as select transistors, the variation of the threshold values thereof can be kept small, and a high and stable reading speed of the flash memory can be readily obtained.
Now, referring to the drawings, a conventional method of manufacturing a 2-Tr type flash memory is described below. FIGS. 3A-3J are schematic cross-sectional views of a semiconductor memory device illustrating, in sequence, the steps of the conventional method.
Firstly, upon a P-type semiconductor substrate 1, a P-well is formed by means of ion implantation and heat treatment. Next, after forming field oxide films 2 in the element isolation regions, a tunnel oxide film 3 is formed to a thickness of 8-10 nm over the surface of the substrate by the thermal oxidation method. This tunnel oxide film constitutes a memory transistor and, at the same time, as a gate oxide film, constitutes a select transistor. Over this film, a first polysilicon 4 that is to serve as a FG is formed to a thickness of 150 nm. Phosphorus is, then, implanted into the first polysilicon 4, which forms an N-type polysilicon (FIG. 3A).
Next, a resist is formed into a pattern in the prescribed region (FIG. 3B), and, using this as a mask, the first polysilicon 4 is etched (FIG. 3C).
Next, by the CVD (Chemical Vapour Deposition) method, an ONO (Oxide-Nitride-Oxide) film 6 is formed over the entire surface of the substrate, to a thickness of 12-16 nm in the terms of oxide film thickness. Further, over this, a second polysilicon 7 is grown to a thickness of 200 nm by the CVD method (FIG. 3D).
Next, in order to form-both gate electrodes of a memory transistor and a select transistor, a resist 8 is formed into patterns (FIG. 3E), and, using the resist 8 as a mask, etching is applied thereto (FIG. 3F).
Next, arsenic or phosphorus is ion implanted thereinto with a dose of 1E 13-14 cm.sup.-2, which forms LDD (Lightly-Doped Drain) regions 9 (FIG. 3G).
Subsequently, an oxide film 10 is grown over the entire surface (FIG. 3H) and, through etch back, sidewalls 11 are formed (FIG. 3I).
Arsenic is, then, ion implanted thereinto with a dose of 1-5 E 15 cm.sup.-2, which forms source-drain regions 12 (FIG. 3J).
The reading speed of the 2-Tr type flash memory is determined by the operational speed of the select transistors therein. Therefore, in order to attain high reading speed, the operational speed of the select transistors must be set high.
In the conventional manufacturing method, however, as the gate oxide film of the select transistor is simultaneously formed with the tunnel oxide film of the memory transistor, the operational speed of the select transistor cannot be designed independently without affecting the memory transistor. As a result, an advantage of high reading speed that the 2-Tr type flash memory possesses in comparison with the 1-Tr type flash memory cannot be, hitherto, exploited to the full.